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wm9708 ac?97 revision 2.1 audio codec advanced information, april 2001, rev 2.0 wolfson microelectronics ltd bernard terrace, edinburgh, eh8 9nx, uk tel: +44 (0) 131 667 9386 fax: +44 (0) 131 667 5176 email: sales@wolfson.co.uk www.wolfsonmicro.com advanced information data sheets contain preliminary data on new products in the preproduction phase of development. supplementary data will be published at a later date. ? 2001 wolfson microelectronics ltd . description wm9708 is a high-quality stereo audio codec compliant with the ac?97 revision 2.1 specification. it performs full duplex 18-bit codec functions and supports variable sample rates from 8 to 48k samples/s and offers excellent quality with high snr. additional features include 3d sound enhancement, line-level outputs, and hardware sample rate conversion. the wm9708 is fully operable on 3.3v or 5v or mixed 3.3/5v supplies, and is packaged in a 28-pin ssop package. ac ? 97 features ? 18-bit stereo codec ? s/n ratio > 95db ? multiple stereo input mixer ? mono and stereo volume control ? power management features ? very low standby power ? variable rate audio (vra) support ? analogue 3d stereo enhancement ? line level outputs ? supports rev. 2.1 specified audio and modem sample rates and filtering ? pc-beep connection when device held reset ? 3.3v or 5v operation ? 28-pin ssop package block diagram vol/ mute vol/ mute vol/ mute vol/ mute (26) monoout (25,56) lineout cd (13,15) linein (17,18) pcbeep (12) mic1 (16) 0db/ 20db (7) bitclk (10) sync (9) sdatain (6) sdataout osc (4) xtlin (5) xtlout vol/ mute stereo dac src vol stereo adc src vol/ mute mux vol/ mute mux key: mono stereo record mux and mute serial i/f vol/ mute (11) resetb wm9708
wm9708 advanced information wolfson microelectronics ltd ai rev 2.0 april 2001 2 pin configuration ordering information device temp. range package xwm9708cds 0 to 70 o c 28-pin ssop 16 15 14 20 19 18 17 5 6 7 1 2 3 4 13 12 11 8 9 10 dvdd cdl mic1 nc nc vrefout lineoutr lineoutl cap nc monoout avdd agnd resetb lineinr xtlout sdataout xtlin sync agnd sdatain dgnd vref bitclk 21 22 23 24 25 26 27 28 pcbeep cdgnd lineinl cdr pin description pin name type description 1 nc no internal connection 2 nc no internal connection 3 dvdd supply digital positive supply 4 xtlin digital input clock crystal connection or clock input (xtal not used) 5 xtlout digital output clock crystal connection 6 sdataout digital input serial data input 7 bitclk digital output serial interface clock output to ac ? 97 controller 8 dgnd supply digital ground supply 9 sdatain digital output serial data output to ac ? 97 controller 10 sync digital input serial interface sync pulse from ac ? 97 controller 11 resetb digital input not reset input (active low, resets registers) 12 pcbeep analogue input mixer input, typically for pcbeep signal 13 cdl analogue input mixer input, typically for cd signal 14 cdgnd analogue input cd input common mode reference (ground) 15 cdr analogue input mixer input, typically for cd signal 16 mic1 analogue input mixer input with extra gain if required 17 lineinl analogue input mixer input, typically for line signal 18 lineinr analogue input mixer input, typically for line signal 19 agnd supply analogue ground supply, chip substrate 20 vref analogue output buffered cap, used as mixer reference 21 vrefout analogue output reference for microphones; buffered cap 22 cap analogue input reference input/output; pulls to midrail if not driven 23 nc no internal connection 24 lineoutl analogue output main analogue output for left channel 25 lineoutr analogue output main analogue output for right channel 26 monoout analogue output main mono output 27 avdd supply analogue positive supply 28 agnd supply analogue ground supply, chip substrate
advanced information wm9708 wolfson microelectronics ltd ai rev 2.0 april 2001 3 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. condition min max digital supply voltage -0.3v +7v analogue supply voltage -0.3v +7v voltage range digital inputs dvss -0.3v dvdd +0.3v voltage range analogue inputs avdd -0.3v avdd +0.3v operating temperature range, t a 0 o c+70 o c storage prior to soldering 30 o c max / 85% rh max storage temperature after soldering -65 o c +150 o c package body temperature (soldering 10 seconds) +240 o c package body temperature (soldering 2 minutes) +183 o c note: 1. the digital supply voltage (dvdd) must always be less than or equal to the analogue supply voltage (avdd). recommended operating conditions parameter symbol test conditions min typ max unit digital supply range dvdd -10% 3.3 to 5.0 +10% v analogue supply range avdd -10% 3.3 to 5.0 +10% v digital ground dgnd 0 v analogue ground agnd 0 v difference dgnd to agnd -0.3 0 +0.3 v analogue supply current dvdd, avdd = 5v 28 ma digital supply current dvdd, avdd = 5v 22 ma standby supply current (all prs set) dvdd, avdd = 5v 10 ua analogue supply current dvdd, avdd = 3.3v 17 ma digital supply current dvdd, avdd = 3.3v 13 ma standby supply current (all prs set) dvdd, avdd = 3.3v 10 ua note: 1. both supplies should be powered on and off at the same time.
wm9708 advanced information wolfson microelectronics ltd ai rev 2.0 april 2001 4 electrical characteristics test characteristics : avdd = 5v, gnd = 0v ???? ..t a = 0 o c to +70 o c, unless otherwise stated dvdd = 3.3v, gnd = 0v ???? ..t a = 0 o c to +70 o c, unless otherwise stated parameter symbol test conditions min typ max unit digital logic levels (dvdd = 3.3 or 5.0v) input low level v il agnd -0.3 0.8 v input high level v ih 2.2 avdd +0.3 v output low v ol 0.10 x vdd v output high v oh 0.90 x vdd v analogue i/o levels (input signals on any inputs, outputs on lineout l, r and monoout) input level minimum input impedance = 10k agnd -100mv avdd +100mv v output level into 10kohm load agnd +300mv near rail to rail avdd -300mv v reference levels reference input/output cap2 2/5 avdd avdd/2 3/5 avdd v cap2 impedance 75 kohms mixer reference vref buffered cap2 v mic reference vrefout buffered cap2 v midbuff current sink (pins vref and vrefout) avdd = 5v -5 -15 ma midbuff current source (pins vref and vrefout) avdd = 5v 5 15 ma midbuff current source (pins vref and vrefout) avdd = 3.3v 10 ma midbuff current sink (pins vref and vrefout) avdd = 3.3v -10 ma dac circuit specifications (avdd = 5v) 48khz sampling snr a-weighted (note 1) 85 95 dbv full scale output voltage vref = 2.5v 1.0 vrms thd -3dbfs input 74 (0.02%) 90 dbv frequency response 20 19,200 hz transition band 19,200 28,800 hz stop band 28,800 hz out of band rejection -40 db spurious tone reduction -100 db psrr 20 to 20khz 40 db adc circuit specifications (avdd = 5v) 48khz sampling snr a-weighted (note 1) 75 92 db adc input for full scale output vref = 2.5v 1.0 vrms thd -6dbv input 74 95 db frequency response 20 19,200 hz transition band 19,200 28,800 hz stop band 28,800 hz stop band rejection -74 db psrr 20 to 20khz 40 db
advanced information wm9708 wolfson microelectronics ltd ai rev 2.0 april 2001 5 test characteristics : avdd = 5v, gnd = 0v ???? ..t a = 0 o c to +70 o c, unless otherwise stated dvdd = 3.3v, gnd = 0v ???? ..t a = 0 o c to +70 o c, unless otherwise stated parameter symbol test conditions min typ max unit mixer circuit specifications (avdd = 5v) 48khz sampling snr cd path a-weighted (note 1) 90 100 db snr other paths a-weighted (note 1) 85 95 db maximum input voltage agnd 1.0 avdd vrms maximum output voltage on lineout 1.0 1.8 vrms thd 0dbv input 74 90 db frequency response (+/-1db) 20 20,000 hz input impedance (cd inputs) at any gain 15 kohm at max gain 10 20 kohm input impedance (other mixer inputs) at 0db gain 50 100 kohm at max gain 10 30 kohm input impedance mic inputs at 0db gain 55 110 kohm psrr 20 to 20khz 50 db dac circuit specifications (avdd = 3.3v) 48khz sampling snr a-weighted (note 1) 92 db full scale output voltage vref = 1.65v 0.7 vrms thd -3dbfs input 85 db frequency response 20 19,200 hz transition band 19,200 28,800 hz stop band 28,800 hz out of band rejection -40 db spurious tone reduction -100 db psrr 20 to 20khz 40 db adc circuit specifications (avdd = 3.3v) 48khz sampling snr a-weighted (note 1) 85 db adc input for full scale output vref = 1.65v 0.7 vrms thd -6dbv input 80 db frequency response 20 19,200 hz transition band 19,200 28,800 hz stop band 28,800 hz stop band rejection -74 db psrr 20 to 20khz 40 db
wm9708 advanced information wolfson microelectronics ltd ai rev 2.0 april 2001 6 test characteristics : avdd = 5v, gnd = 0v ???? ..t a = 0 o c to +70 o c, unless otherwise stated dvdd = 3.3v, gnd = 0v ???? ..t a = 0 o c to +70 o c, unless otherwise stated parameter symbol test conditions min typ max unit mixer circuit specifications (avdd = 3.3v) 48khz sampling snr cd path a-weighted (note 1) 95 db snr other paths a-weighted (note 1) 90 db maximum input voltage 0.6 vrms maximum output voltage on lineout 1.2 vrms thd (note 2) -3.6dbv input 85 dbv frequency response (+/-1db) 20 20,000 hz input impedance (cd inputs) at any gain 15 kohm at max gain 20 kohm input impedance (other mixer inputs) at 0db gain 100 kohm at max gain 30 kohm input impedance mic inputs at 0db gain 110 kohm psrr 20 to 20khz 50 db clock frequency range crystal clock 24.576 mhz bitclk frequency 12.288 mhz sync frequency 48.0 khz notes: 1. snr is the ratio of 0db signal output to the output level with no signal, measured a-weighted over a 20hz to 20khz bandwidth. 2. inputs are scaled for avdd eg; 0dbv at 5.0v is equivalent to ? 3.6dbv at 3.3v.
advanced information wm9708 wolfson microelectronics ltd ai rev 2.0 april 2001 7 detailed timing diagrams test characteristics : avdd = 5v, gnd = 0v ???? ..t a = 0 o c to +70 o c, unless otherwise stated. dvdd = 3.3v, gnd = 0v ???? ..t a = 0 o c to +70 o c, unless otherwise stated. all measurements are taken at 10% to 90% vdd, unless otherwise stated. all the following timing information is guaranteed, not tested. ac-link low power mode sync bitclk sdataout write to 0x20 data pr4 don ? t care sdatain slot 1 slot 2 t s2_pdown figure 1 ac-link powerdown timing parameter symbol min typ max unit end of slot 2 to bitclk sdatin low t s2_pdown 1.0 s cold reset resetb bitclk t rst_low t rst2clk figure 2 cold reset timing parameter symbol min typ max unit resetb active low pulse width t rst_low 1.0 s resetb release (or rising edge) to bitclk startup delay t rst2_clk 162.8 ns
wm9708 advanced information wolfson microelectronics ltd ai rev 2.0 april 2001 8 warm reset sync bitclk t sync_high t sync2clk figure 3 warm reset timing parameter symbol min typ max unit sync active high pulse width t sync_high 1.3 s sync release (or falling edge) to bitclk startup delay t sync2_clk 162.4 ns clock specifications bitclk sync t clk_high t clk_low t clk_period t sync_high t sync_low t sync_period figure 4 clock specifications (50pf external load) parameter symbol min typ max unit bitclk frequency 12.288 mhz bitclk period t clk_period 81.4 ns bitclk output jitter 750 ps bitclk high pulse width (see note) t clk_high 32.56 40.7 48.84 ns bitclk low pulse width (see note) t clk_low 32.56 40.7 48.84 ns sync frequency 48.0 khz sync period t sync_period 20.8 s sync high pulse width t sync_high 1.3 s sync low pulse width t sync_low 19.5 s note: worst case duty cycle restricted to 40/60.
advanced information wm9708 wolfson microelectronics ltd ai rev 2.0 april 2001 9 data setup and hold (50pf external load) bitclk sdataout sync t setup t hold figure 5 data setup and hold (50pf external load) note: setup and hold time parameters for sdata_in are with respect to ac ? 97 controller. parameter symbol min typ max unit setup to falling edge of bitclk t setup 15.0 ns hold from falling edge of bitclk t hold 5.0 ns signal rise and fall times bitclk sync sdatain sdataout t rise clk t fall clk t rise sync t fall sync t rise din t fall din t rise dout t fall dout figure 6 signal rise and fall times (50pf external load) parameter symbol min typ max unit bitclk rise time trise clk 26ns bitclk fall time tfall clk 26ns sync rise time trise sync 26ns sync fall time tfall sync 26ns sdatain rise time trise din 26ns sdatain fall time trise din 26ns sdataout rise time trise dout 26ns sdataout fall time tfall dout 26ns
wm9708 advanced information wolfson microelectronics ltd ai rev 2.0 april 2001 10 system information wm9708 ac ? 97 digital controller resetb bitclk sync sdatain sdataout pcbeep cd, lineinl/r mono_out lineoutl/r mic1 26 25 12 16 11 7 10 9 6 24 figure 7 revision 2.1 compliant 2-channel codec device description introduction the wm9708 comprises a stereo 18-bit codec, (that is, 2 adcs and 2 dacs) a comprehensive analogue mixer with 2 sets of stereo inputs, phone, microphone, and pc-beep inputs. additionally, on-chip reference generation circuits generate the necessary bias voltages for the device, and a bi- directional serial interface allows transfer of control data and dac and adc words to and from the ac ? 97 controller. the wm9708 supports 18-bit resolution within the dac and adc functions, but the ac ? 97 serial interface specification allows any word length up to 20-bits to be written to, or read from, the ac ? 97 codec. these words are msb justified, and any lsbs not used will simply default to 0. normally it is anticipated that 16-bit words will be used in most pc type systems. therefore, for the dac, 16-bit words will be downloaded into the codec from the controller, along with padding of 0s to make the 16-bit word up to 20-bit length. in this case, the wm9708 will process the 16-bit word along with 0 padding bits in the 2 lsb locations (to make 18-bit). at the adc output, wm9708 will provide an 18-bit word, again with 0s in the two lsb locations (20-bit). the ac ? 97 controller will then ignore the 4 lsbs of the 20-bit word. when the wm9708 is interrogated at register 00h, it responds indicating it is an 18-bit device. the wm9708 has the adc and dac functions implemented using oversampled, or sigma-delta converters, and uses on-chip digital filters to convert these 1-bit signals to and from the 48ks/s 16/18- bit pcm words that the ac ? 97 controller requires. the digital parts of the device are powered separately from the analogue to optimise performance, and 3.3v digital and 5v analogue supplies may be used on the same device to further optimise performance. digital i/os are 5v tolerant when the analogue supplies are 5v, so the wm9708 may be connected to a controller running on 5v supplies, but use 3.3v for the digital section of wm9708. wm9708 is also capable of operating with a 3.3v supply only (digital and analogue). an internally generated midrail reference is provided at pin cap which is used as the chip reference. this pin should be heavily decoupled. refer to figure 15 for more details. the wm9708 is not limited to pc-only applications. the ability to power down sections of the device selectively, and the option to choose alternative master clock, and hence sample rates, means that many alternative applications in areas such as telecoms, may be anticipated. additional features added to the intel ac ? 97 2.1 specification, such as the internal connection of pc- beep to the outputs in the case where the device is reset, are supported, along with optional features such as variable sample rate support.
advanced information wm9708 wolfson microelectronics ltd ai rev 2.0 april 2001 11 variable sample rate support the dacs and adcs on this device support all the recommended sample rates specified in the intel revision 2.1 specification for audio rates. the default rate is 48ks/s. if alternative rates are selected and variable rate audio is enabled (register 2ah, bit 0), the ac ? 97 interface continues to run at 48k words per second, but data is transferred across the link in bursts such that the net sample rate selected is achieved. it is up to the ac ? 97 revision 2.1 compliant controller to ensure that data is supplied to the ac link, and received from the ac link, at the appropriate rate. the device supports on demand sampling. that is, when the dac signal processing circuits need another sample, a sample request is sent to the controller which must respond with a data sample in the next frame it sends. for example, if a rate of 24ks/s is selected, on average the device will request a sample from the controller every other frame, for each of the stereo dacs. note that if an unsupported rate is written to one of the rate registers, the rate will default to the nearest rate supported. the register will then respond when interrogated with the default sample rate. the left and right channels of the adcs and dacs always sample at the same rate. audio sample rate control value d15-d0 8000 1f40 11025 2b11 16000 3e80 22050 5622 32000 7d00 44100 ac44 48000 bb80 table 1 variable sample rates supported gain control register location pga control register mute default dac 18h muted (bit-15) mixer 72h not-muted (bit-15) volume 02h muted (15) table 2 gain control register location master support wm9708 supports operation as a master codec. fundamentally, a device identified as a master produces a bitclk as an input. control interface a digital interface has been provided to control the wm9708 and transfer data to and from it. this serial interface is compatible with the intel ac ? 97 specification. the main control interface functions are: ? control of analogue gain and signal paths through the mixer ? bi-directional transfer of adc and dac words to and from ac ? 97 controller ? selection of powerdown down modes.
wm9708 advanced information wolfson microelectronics ltd ai rev 2.0 april 2001 12 ac-link digital serial interface protocol the wm9708 incorporates a 5-pin digital serial interface that links it to the ac ? 97 controller. the ac- link is a bi-directional, fixed rate, serial pcm digital stream. it handles multiple input and output audio streams, as well as control register accesses, employing a time division multiplexed (tdm) scheme. the ac-link architecture divides each audio frame into 12 outgoing and 12 incoming data streams, each with 20-bit sample resolution and a 16-bit header slot. with a minimum required dac and adc resolution of 16-bits, ac ? 97 may also be implemented with 18 or 20-bit dac/adc resolution, given the headroom that the ac-link architecture provides. the wm9708 provides support for 18-bit operation. slot number sync sdataout s d a t a i n tag phase tag cmd adr cmd data pcm left pcm right rsrvd rsrvd rsrvd tag status addr status data pcm left pcm right rsrvd rsrvd rsrvd rsrvd rsrvd rsrvd rsrvd data phase 0123456789101112 pcm c (n+1) pcm r (n+1) pcm l (n+1) codec id slotreq 3-12 pcm centre rsrvd pcm l surr pcm r surr pcm lfe rsrvd figure 8 ac ? 97 standard bi-directional audio frame sync bitclk sdataout valid frame slot(1) slot(2) slot(12) ? 0 ? (id1) (id0) 19 0 19 0 19 0 19 0 tag phase data phase 20.8 s (48khz) 12.288mhz 81.4ns end of previous audio frame time slot ? valid ? bits ( ? 1 ? = time slot contains valid pcm data) slot (1) slot (2) slot (3) slot (12) figure 9 ac-link audio output frame
advanced information wm9708 wolfson microelectronics ltd ai rev 2.0 april 2001 13 the datastreams currently defined by the ac ? 97 specification include: pcm playback - 2 output slots 2-channel composite pcm output stream pcm record data - 2 input slots 2-channel composite pcm input stream control - 2 output slots control register write port status - 2 input slots control register read port optional modem line codec output - 1 output slot modem line codec dac input stream optional modem line codec input ? 1 input slot modem line codec adc output stream optional dedicated microphone input - 1 input slot dedicated microphone input stream in support of stereo aec and/or other voice applications. synchronisation of all ac-link data transactions is signalled by the wm9708 controller. the wm9708 drives the serial bit clock onto ac-link, which the ac ? 97 controller then qualifies with a synchronisation signal to construct audio frames. sync, fixed at 48khz, is derived by dividing down the serial clock (bitclk). bitclk, fixed at 12.288mhz, provides the necessary clocking granularity to support 12, 20-bit outgoing and incoming time slots and the tag slot. ac-link serial data is transitioned on each rising edge of bitclk. the receiver of ac-link data, (wm9708 for outgoing data and ac ? 97 controller for incoming data), samples each serial bit on the falling edges of bitclk. the ac-link protocol provides for a special 16-bit time slot (slot 0) wherein each bit conveys a valid tag for its corresponding time slot within the current audio frame. a 1 in a given bit position of slot 0 indicates that the corresponding time slot within the current audio frame has been assigned a data stream, and contains valid data. if a slot is tagged invalid, it is the responsibility of the source of the data, (the wm9708 for the input stream, ac ? 97 controller for the output stream), to stuff all bit positions with 0s during that slot ? s active time. sync remains high for a total duration of 16 bitclks at the beginning of each audio frame. the portion of the audio frame where sync is high is defined as the tag phase. the remainder of the audio frame where sync is low is defined as the data phase. additionally, for power savings, all clock, sync, and data signals can be halted. this requires that the wm9708 be implemented as a static design to allow its register contents to remain intact when entering a power savings mode. ac-link audio output frame (sdata_out) the audio output frame data streams correspond to the multiplexed bundles of all digital output data targeting the wm9708 ? s dac inputs, and control registers. as briefly mentioned earlier, each audio output frame supports up to 12 20-bit outgoing data time slots. slot 0 is a special reserved time slot containing 16-bits, which are used for ac-link protocol infrastructure. output tag slot (16-bits) bit (15) frame valid bit (14) slot 1 valid command address bit (primary codec only) bit (13) slot 2 valid command data bit (primary codec only) bit (12:3) slot 3-12 valid bits as defined by ac ? 97 bit 2 reserved (set to 0) bit (1:0) 2-bit message id field (00 reserved for primary; 01 indicates secondary) within slot 0 the first bit is a global bit (sdataout slot 0, bit 15) which flags the validity for the entire audio frame. if the valid frame bit is a 1, this indicates that the current audio frame contains at least one time slot of valid data. the next 12-bit positions sampled by the wm9708 indicate which of the corresponding 12 time slots contain valid data. it should be noted that in ura, even when slot 1 is tagged as invalid, the request bits are still valid. in this way data streams of differing sample rates can be transmitted across ac-link at its fixed 48khz audio frame rate. figure 9 illustrates the time slot based ac-link protocol.
wm9708 advanced information wolfson microelectronics ltd ai rev 2.0 april 2001 14 when the codec is a slave device, bits 14 and 13 are not used to validate data in slots 1 and 2. instead, if the message id bits (1:0) match the codec id then the address is valid and bit 19 from slot 1 then indicates if slot 2 is valid. sync bit_clk sdata_out valid frame slot (1) slot (2) wm9707 samples sync assertion here wm9707 samples first sdata_out bit of frame here end of previous audio frame figure 10 start of an audio output frame a new audio output frame begins with a low to high transition of sync as shown in figure 10. sync is synchronous to the rising edge of bitclk. on the immediately following falling edge of bitclk, the wm9708 samples the assertion of sync. this falling edge marks the time when both sides of ac-link are aware of the start of a new audio frame. on the next rising edge of bitclk, ac ? 97 transitions sdataout into the first bit position of slot 0 (valid frame bit). each new bit position is presented to ac-link on a rising edge of bitclk, and subsequently sampled by the wm9708 on the following falling edge of bitclk. this sequence ensures that data transitions and subsequent sample points for both incoming and outgoing data streams are time aligned. baseline ac ? 97 specified audio functionality must always sample rate convert to and from a fixed 48ks/s on the ac ? 97 controller. this requirement is necessary to ensure that interoperability between the ac ? 97 controller and the wm9708, among other things, can be guaranteed by definition for baseline specified ac ? 97 features. sdataout ? s composite stream is msb justified (msb first) with all non-valid slot bit positions stuffed with 0s by the ac ? 97 controller. in the event that there are less than 20 valid bits within an assigned and valid time slot, the ac ? 97 controller always stuffs all trailing non-valid bit positions of the 20-bit slot with 0s.
advanced information wm9708 wolfson microelectronics ltd ai rev 2.0 april 2001 15 as an example, consider an 8-bit sample stream that is being played out to one of the wm9708 ? s dacs. the first 8 bit positions are presented to the dac (msb justified) followed by the next 12 bit positions, which are stuffed with 0s by the ac ? 97 controller. this ensures that regardless of the resolution of the implemented dac (16, 18 or 20-bit), no dc biasing will be introduced by the least significant bits. when mono audio sample streams are output from the ac ? 97 controller, it is necessary that both left and right sample stream time slots be filled with the same data. slot 1: command address port the command port is used to control features, and monitor status for the wm9708 functions including, but not limited to, mixer settings, and power management (refer to the serial interface register map). the control interface architecture supports up to 128, 16-bit read/write registers, however only those addressable on even byte boundaries are used in rev 2.1. only the even registers (00h, 02h, etc.) are valid. odd register read/write will have no effect on the wm9708. audio output frame slot 1 communicates control register address, and read/write command information to the wm9708. command address port bit assignments bit (19) read/write command (1 = read, 0 = write) bit (18:12) control register index (64 16-bit locations, addressed on even byte boundaries) bit (11:0) reserved (stuffed with 0s) the first bit (msb) sampled by the wm9708 indicates whether the current control transaction is a read or write operation. the following 7 bit positions communicate the targeted control register address. the trailing 12 bit positions within the slot are reserved and must be stuffed with 0s by the ac ? 97 controller. slot 2: command data port the command data port is used to deliver 16-bit control register write data in the event that the current command port operation is a write cycle. (as indicated by slot 1, bit 19). bit (19:4) control register write data (stuffed with 0s if current operation is a read) bit (3:0) reserved (stuffed with 0s) if the current command port operation is a read then the entire time slot must be stuffed with 0s by the ac ? 97 controller. slot 3: pcm playback left channel audio output frame slot 3 is the composite digital audio left playback stream. in a typical games compatible pc this slot is composed of standard pcm (.wav) output samples digitally mixed (on the ac ? 97 controller or host processor) with music synthesis output samples. if a sample stream of resolution less than 20-bits is transferred, the ac ? 97 controller must stuff all trailing non-valid bit positions within this time slot with 0s. slot 4: pcm playback right channel audio output frame slot 4 is the composite digital audio right playback stream. in a typical games compatible pc this slot is composed of standard pcm (.wav) output samples digitally mixed (on the ac ? 97 controller or host processor) with music synthesis output samples. if a sample stream of resolution less than 20-bits is transferred, the ac ? 97 controller must stuff all trailing non-valid bit positions within this time slot with 0s. slot 5: optional modem line codec audio output frame slot 5 contains the msb justified modem dac input data. this optional ac ? 97 feature is not supported in the wm9708, and if data is written to this location it is ignored. this may be determined by the ac ? 97 controller interrogating the wm9708 reg 28h and 3ch.
wm9708 advanced information wolfson microelectronics ltd ai rev 2.0 april 2001 16 slots 6 to 9: surround sound data audio output frame slots 6 to 9 are used to send surround sound data. unsupported by wm9708. slots 10 and 11: line2 and handset dac these data slots are not supported. slot 12: gpio control these data slots are not supported. ac-link audio input frame (sdata_in) sync bitclk sdatain codec ready slot(1) slot(2) slot(12) ? 0 ? ? 0 ? ? 0 ? 19 0 19 0 19 0 19 0 tag phase data phase 20.8 s (48khz) 12.288mhz 81.4ns end of previous audio frame time slot ? valid ? bits ( ? 1 ? = time slot contains valid pcm data) slot (1) slot (2) slot (3) slot (12) figure 11 ac-link audio input frame the audio input frame data streams correspond to the multiplexed bundles of all digital input data targeting the ac ? 97 controller. as is the case for audio output frame, each ac-link audio input frame consists of 12, 20-bit time slots plus the tag slot. slot 0 is a special reserved time slot containing 16-bits, which are used for ac-link protocol infrastructure. within slot 0 the first bit is a global bit (sdatain slot 0, bit 15) which flags whether the wm9708 is in the codec ready state or not. if the codec ready bit is a 0, this indicates that the wm9708 is not ready for normal operation. this condition is normal following the desertion of power on reset for example, while the wm9708 ? s voltage references settle. when the ac-link codec ready indicator bit is a 1, it indicates that the ac-link and the wm9708 control and status registers are in a fully operational state. the ac ? 97 controller must further probe the powerdown control/status register to determine exactly which subsections, if any, are ready. prior to any attempts at putting the wm9708 into operation the ac ? 97 controller should poll the first bit in the audio input frame (sdatain slot 0, bit 15) for an indication that the wm9708 has gone codec ready. once the wm9708 is sampled codec ready then the next 12 bit positions sampled by the ac ? 97 controller indicate which of the corresponding 12 time slots are assigned to input data streams, and that they contain valid data. figure 11 illustrates the time slot based ac-link protocol. there are several subsections within the wm9708 that can independently go busy/ready. it is the responsibility of the wm9708 controller to probe more deeply into the wm9708 register file to determine which the wm9708 subsections are actually ready.
advanced information wm9708 wolfson microelectronics ltd ai rev 2.0 april 2001 17 sync bitclk sdatain the wm9707 samples sync assertion here ac ? 97 controller samples first sdata_in bit of frame here end of previous audio frame codec ready slot (1) slot (2) figure 12 start of an audio input frame a new audio input frame begins with a low to high transition of sync as shown in figure 12. sync is incident with the rising edge of bitclk. on the immediately following falling edge of bitclk, ac ? 97 samples the assertion of sync. this falling edge marks the time when both sides of ac-link are aware of the start of a new audio frame. on the next rising of bitclk, ac ? 97 transitions sdatain into the first bit position of slot 0 ( ? codec ready ? bit). each new bit position is presented to ac-link on a rising edge of bitclk, and subsequently sampled by the ac ? 97 controller on the following falling edge of bitclk. this sequence ensures that data transitions and subsequent sample points for both incoming and outgoing data streams are time aligned. sdatain ? s composite stream is msb justified (msb first) with all non-valid bit positions (for assigned and/or unassigned time slots) stuffed with 0s by the wm9708. sdatain should be sampled on the falling edges of bitclk. slot 1: status address port the status port is used to monitor status for the wm9708 functions including, but not limited to, mixer settings, and power management. audio input frame slot 1 echoes the control register index, for historical reference, for the data to be returned in slot 2. (assuming that slots 1 and 2 had been tagged valid by the wm9708 during slot 0). status address port bit assignments : bit (19) reserved (stuffed with 0s) bit (18:12) control register index (echo of register index for which data is being returned) bit (11:2) variable sample rate slotreq bits. bit (1:0) reserved (stuffed with 0s) the first bit (msb) generated by the wm9708 is always stuffed with a 0. the following 7 bit positions communicate the associated control register address. the next 10 bits support the ac ? 97 rev 2.1 variable sample rate signalling protocol, and the trailing 2 bit positions are stuffed with 0s by ac ? 97. in vra the slot requests in slot 1 (bits 11-3) are always valid regardless of slot tag. slot 2: status data port the status data port delivers 16-bit control register read data. bit (19:4) control register read data (stuffed with 0s if tagged invalid by wm9701) bit (3:0) reserved (stuffed with 0s) if slot 2 is tagged invalid by the wm9708, then the entire slot will be stuffed with 0s by the wm9708. slot 3: pcm record left channel audio input frame slot 3 is the left channel output of the wm9708 ? s input mux, post-adc. the wm9708 sends out its adc output data (msb first), and stuffs any trailing non-valid bit positions with 0s to fill out its 20-bit time slot.
wm9708 advanced information wolfson microelectronics ltd ai rev 2.0 april 2001 18 slot 4: pcm record right channel audio input frame slot 4 is the right channel output of the wm9708 ? s input mux, post-adc. the wm9708 ? s adcs can be implemented to support 16, 18, or 20-bit resolution. the wm9708 ships out its adc output data (msb first), and stuffs any trailing non-valid bit positions with 0s to fill out its 20-bit time slot. slot 5: optional modem line codec not supported by wm9708. slot 6: optional dedicated microphone record data not supported by wm9708. slots 7 to 12: reserved audio input frame slots 7 to 12 are reserved for future use and are always stuffed with 0s by the wm9708. ac-link low power mode the ac-link signals can be placed in a low power mode. when the wm9708 ? s powerdown register 26h, is programmed to the appropriate value, both bitclk and sdatain will be brought to, and held at a logic low voltage level. bitclk and sdatain are transitioned low immediately following the decode of the write to the powerdown register 26h with pr4. when the ac ? 97 controller driver is at the point where it is ready to program the ac-link into its low power mode, slots 1 and 2 are assumed to be the only valid stream in the audio output frame. at this point in time it is strongly recommended that all sources of audio input have also been neutralised. the ac ? 97 controller should also drive sync and sdataout low after programming the wm9708 to this low power, halted mode. once the wm9708 has been instructed to halt bitclk, a special wake up protocol must be used to bring the ac-link to the active mode since normal audio output and input frames can not be communicated in the absence of bitclk. waking up the ac-link there are 2 methods for bringing the ac-link out of a low power, halted mode. regardless of the method, it is the ac ? 97 controller that performs the wake up task. ac-link protocol provides for a cold wm9708 reset, and a warm wm9708 reset. the current powerdown state would ultimately dictate which form of wm9708 reset is appropriate. unless a cold or register reset (a write to the reset register 00h) is performed, wherein the wm9708 registers are initialised to their default values, registers are required to keep state during all powerdown modes. once powered down, re-activation of the ac-link via re-assertion of the sync signal must not occur for a minimum of 4 audio frame times following the frame in which the powerdown was triggered. when ac-link powers up it indicates readiness via the codec ready bit (input slot 0, bit 15). cold wm9708 reset a cold reset is achieved by asserting resetb for the minimum specified time (1 s). by driving resetb low, bitclk, and sdataout will be activated, or re-activated as the case may be, and all the wm9708 control registers will be initialised to their default power on reset values. resetb is an asynchronous wm9708 input. see figure 2.
advanced information wm9708 wolfson microelectronics ltd ai rev 2.0 april 2001 19 warm wm9708 reset a warm wm9708 reset will re-activate the ac-link without altering the current wm9708 register values. a warm reset is signalled by driving sync high for a minimum of 1 s in the absence of bitclk. see figure 3. within normal audio frames sync is a synchronous input. in the absence of bitclk, sync is treated as an asynchronous input used in the generation of a warm reset to the wm9708. the wm9708 will not respond with the activation of bitclk until sync has been sampled low again by the wm9708. this will preclude the false detection of a new audio frame. serial interface register map description (see table 15) the serial interface bits perform control functions described as follows: the register map is fully specified by the ac ? 97 specification, and this description is simply repeated below, with optional unsupported features omitted. reset register (index 00h) writing any value to this register performs a register reset, which causes registers 0-2b inclusive to revert to their default values. reading this register returns the id code of the part, indication of modem support (not supported by the wm9708) and a code for the type of 3d stereo enhancement (not supported by the wm9708). the id decodes the capabilities of the wm9708 based on the following: bit function value on wm9708 id0 dedicated mic pcm in channel 0 id1 modem line codec support 0 id2 bass and treble control 0 id3 simulated stereo (mono to stereo) 0 id4 headphone out support 1 id5 loudness (bass boost) support 0 id6 18-bit dac resolution 1 id7 20-bit dac resolution 0 id8 18-bit adc resolution 1 id9 20-bit adc resolution 0 se4...se0 no 3d support 00000 table 3 reset register function note that the wm9708 defaults to indicate 18-bit compatibility. play master volume registers (index 02h, 04h and 06h) these registers manage the output signal volumes. register 02h controls the stereo master volume (both right and left channels), register 04h controls the optional stereo headphone out, and register 06h controls the mono volume output. each step corresponds to 1.5db. the msb of the register is the mute bit. when this bit is set to 1 the level for that channel is set at - db. ml5 to ml0 is for left channel level, mr5 to mr0 is for the right channel and mm5 to mm0 is for the mono out channel. support for the msb of the volume level is not provided by the wm9708. if the msb is written to, then the wm9708 detects when that bit is set and sets all 4 lsbs to 1s. example: if the driver writes a 1xxxxx the wm 9708 interprets that as x11111. it will also respond when read with x11111 rather than 1 xxxxx, the value written to it. the driver can use this feature to detect if s upport for the 6th bit is there or not. the default value of both the mono and the stereo registers is 8000h (1000 0000 0000 0000), which corresponds to 0db gain with mute on.
wm9708 advanced information wolfson microelectronics ltd ai rev 2.0 april 2001 20 mute mx4...mx0 f unction 0 0 0000 0db attenuation 0 0 0001 1.5db attenuation 0 1 1111 46.5db attenuation 1 x xxxx db attenuation table 4 volume register function master tone control registers (index 08h) optional register for support of tone controls (bass and treble). the wm9708 does not support bass and treble and writing to this register will have no effect, reading will result in all zeros. pc beep register (index 0ah) this controls the level for the pc-beep input. each step corresponds to approximately 3db of attenuation. the msb of the register is the mute bit. when this bit is set to 1 the level for that channel is set at - db. wm9708 defaults to the pc-beep path being muted, except during reset when the path is open, so an external speaker should be provided within the pc to alert the user to power on self-test problems. mute pv3...pv0 function 0 0000 0db attenuation 0 1111 45db attenuation 1 xxxx db attenuation table 5 pc-beep register function analogue mixer input gain registers (index 0ch - 18h and 72h) this controls the gain/attenuation for each of the analogue inputs and mixer pga. each step corresponds to approximately 1.5db. the msb of the register is the mute bit. when this bit is set to 1 the level for that channel is set at - db. register 0eh (mic volume register) this has an extra bit that is for a 20db boost. when bit 6 is set to 1 the 20db boost is on. the default value is 8008h, which corresponds to 0db gain with mute on. the default value for the mono registers is 8008h, which corresponds to 0db gain with mute on. the default value for stereo registers is 8808h, which corresponds to 0db gain with mute on. mute gx4...gx0 f unction 0 00000 +12db gain 0 01000 0db gain 0 11111 -34.5db gain 1 xxxxx - db gain table 6 mixer gain control register function record select control register (index 1ah) used to select the record source independently for right and left (see table 7). the default value is 0000h, which corresponds to mic in.
advanced information wm9708 wolfson microelectronics ltd ai rev 2.0 april 2001 21 sr2 to sr0 right record source sl2 to sl0 left record source 0 mic 0 mic 1 cd in (r) 1 cd in (l) 2 not supported 2 not supported 3 not supported 3 not supported 4 line in (r) 4 line in (l) 5 stereo mix (r) 5 stereo mix (l) 6 mono mix 6 mono mix 7 phone 7 phone table 7 record select register function record gain registers (index 1ch) 1ch is for the stereo input. each step corresponds to 1.5db. 22.5db corresponds to 0f0fh. the msb of the register is the mute bit. when this bit is set to 1, the level for that channel(s) is set at - db. the default value is 8000h, which corresponds to 0db gain with mute on. mute gx3...gx0 f unction 0 1111 +22.5db gain 0 0000 0db gain 1 xxxxx - db gain table 8 record gain register function general purpose register (index 20h) this register is used to control several miscellaneous functions of the wm9708. below is a summary of each bit and its function. only the mix, ms and lpbk bits are supported by the wm9708. the ms bit controls the mic selector. the lpbk bit enables loopback of the adc output to the dac input without involving the ac-link, allowing for full system performance measurements. the function default value is 8000h which is all off. bit function wm9708 support pop pcm out path and mute yes st simulated stereo enhancement, on/off 1 = on no 3d 3d stereo enhancement on/off, 1 = on no ld loudness (bass boost) on/off, 1 = on no llbk local loop back - for modem, line codec no rlbk remote loop back - for modem, line codec no mix mono output select 0 = mix, 1 = mic yes ms mic select 0 = mic1, 1 = mic2 yes lpbk adc/dac loopback mode yes table 9 general purpose register function
wm9708 advanced information wolfson microelectronics ltd ai rev 2.0 april 2001 22 powerdown control/status register (index 26h) this read/write register is used to program powerdown states and monitor subsystem readiness. the lower half of this register is read only status, a 1 indicating that the subsection is ready . ready is defined as the subsection able to perform in its nominal state. when this register is written the bit values that come in on ac-link will have no effect on read only bits 0 to 7. when the ac-link codec ready indicator bit (sdatain slot 0, bit 15) is a 1 it indicates that the ac- link and the wm9708 control and status registers are in a fully operational state. the ac ? 97 controller must further probe this powerdown control/status register to determine exactly which subsections, if any, are ready. read bit function ref vrefs up to nominal level anl analogue mixers, etc ready dac dac section ready to accept data adc adc section ready to transmit data table 10 powerdown status register function the powerdown modes are as follows. the first three bits are to be used individually rather than in combination with each other. the last bit pr3 can be used in combination with pr2 or by itself. pr0 and pr1 control the pcm adcs and dacs only. pr6 is not supported by the wm9708. write bit function pr0 pcm in adcs and input mux powerdown pr1 pcm out dacs powerdown pr2 analogue mixer powerdown (vref still on) pr3 analogue mixer powerdown (vref off) pr4 digital interface (ac-link) powerdown (external clock off) pr5 internal clock disable pr6 hp amp powerdown ? not supported eapd external amplifier powerdown table 11 powerdown control register function pr0 = 1 pr1 = 1 pr2 = 1 pr4 = 1 pr0 = 0 and adc = 1 default ready = 1 cold reset warm reset pr2 = 0 and anl = 1 pr1 = 0 and dac = 1 adcs off pr0 dacs off pr1 analogue off pr2 or pr3 digital i/f off pr4 shut off coda link normal figure 13 an example of the wm9708 powerdown/powerup flow figure 13 illustrates one example procedure to do a complete powerdown of the wm9708. from normal operation sequential writes to the powerdown register are performed to powerdown the wm9708 a piece at a time. after everything has been shut off (pr0 to pr3 set), a final write (of pr4) can be executed to shut down the wm9708 ? s digital interface (ac-link).
advanced information wm9708 wolfson microelectronics ltd ai rev 2.0 april 2001 23 the part will remain in sleep mode with all its registers holding their static values. to wake up the wm9708, the ac ? 97 controller will send a pulse on the sync line issuing a warm reset. this will restart the wm9708 ? s digital interface (resetting pr4 to 0). the wm9708 can also be woken up with a cold reset. a cold reset will cause a loss of values of the registers, as a cold reset will set them to their default states. when a section is powered back on, the powerdown control/status register (index 26h) should be read to verify that the section is ready (i.e. stable) before attempting any operation that requires it. pr1 = 1 pr2 = 1 pr4 = 1 adcs off pr0 dacs off pr1 analogue off pr2 or pr3 digital i/f off pr4 warm reset pr1 = 0 and dac = 1 pr2 = 0 and anl = 1 shut off coda link figure 14 the wm9708 powerdown/flow with analogue still alive figure 14 illustrates a state when all the mixers will work with the static volume settings that are contained in their associated registers. this is used when the user could be playing a cd (or external linein source) through wm9708 to the speakers but have most of the system in low power mode. the procedure for this follows the previous except that the analogue mixer is never shut down. powerdown control/status register (index 26h) note that in order to go into ultimate low power mode, pr4 and pr5 are required to be set which turns off the oscillator circuit. asserting sync resets the pr4 and pr5 bit and re-starts the oscillator in the same was as the ac link is restarted. revision 2.1 registers (index 28h t0 58h) these registers are specified as to use in revision 2.1 of the ac ? 97 specification and have the following functions on the wm9708: register 28h ? extended audio id the extended audio id register is a read only register that identifies which extended audio features are supported (in addition to the original ac ? 97 features identified by reading the reset register at index 00h). a non zero value indicates the feature is supported. data bit function any mode vra variable rate audio support 1 dra double rate audio support 0 vrm variable rate mic adc support 0 cdac centre dac support 0 sdac surround dac support 0 ldac lfe dac support 0 amap slot to front dac mapping support 0 id1 codec configuration ? fixed in 9707 0 id0 not supported not supported table 12 extended audio id register
wm9708 advanced information wolfson microelectronics ltd ai rev 2.0 april 2001 24 register 2ah ? extended audio status and control register the extended audio status and control register is a read/write register that provides status and control of the extended audio features. data bit function read/write wm9708 support vra enables variable rate audio mode read/write yes dra enable double rate audio mode read/write no vrm enables variable rate mic adc read/write no cdac indicates centre dac ready read no sdac indicates surround dac ready read no ldac indicates lfe dac ready read no madc indicates mic adc ready read no pri set to turn off centre dac read/write no prj set to turn off surround dacs read/write no prk set to turn off lfe dacs read/write no prl set to turn off mic adc read/write no table 13 extended audio status and control register register 2ch to 32h ? audio sample rate control registers these registers are read/write registers that are written to, to select alternative sample rates for the audio pcm converters. default is the 48ks/s rate. note that only revision 2.1 recommended rates are supported by the wm9708, selection of any other unsupported rates will cause the rate to default to the nearest supported rate, and the supported rate value to be latched and so read back. registers 36h and 38h ? 6 channel volume control these read/write registers control the output volume of the optional four pcm channels. (not supported by the wm9708) vendor reserved registers (index 5ah - 7ah) these registers are vendor specific. do not write to these registers unless the vendor id register has been checked first to ensure that the driver knows the source of the ac ? 97 component. vendor specific register (index 5ch) the wm9708 can be programmed to automute the dacs. by setting the mute bit, the wm9708 will mute the dacs when it detects a continuous sequence of 1024 zeros. vendor specific gain control registers ? (index 72h) this register controls the gain and mute functions applied to the mixer path. this pga is not accommodated in the intel specification, but is required in order to allow the option of simultaneous recording of the mixer output and playback of dac signals. the function is as per the other mixer pga ? s. however, the default value of the register is not-muted. if it is not used it will be transparent to the user. vendor id registers (index 7ch to 7eh) this register is for specific vendor identification if so desired. the id method is microsoft ? s plug and play vendor id code. the first character of that id is f7 to f0, the second character s7 to s0, and the third t7 to t0. these three characters are ascii encoded. the rev7 to rev0 field is for the vendor revision number. in the wm9708 the vendor id is set to wml3. wolfson is a registered microsoft plug and play vendor. vendor id registers (index 74h) this register describes how data is mapped to the ac ? 97 dacs. register 74h can be used to change the incoming dac data slots that are used by the on-board dacs. this allows software control of multiple codecs. if used it is recommended that the id is configured before any other registers and before the data is applied to the system.
advanced information wm9708 wolfson microelectronics ltd ai rev 2.0 april 2001 25 surround sound dss1, dss0 pcm out left pcm out right 00 3 4 01 7 8 1x 6 9 table 14 vendor id registers - reg 74 [1:0] this allows the user to connect multiple codecs to a host controller using a single ac-link interface. the volume control register is still 02h and the rate register is 2ch. the id pins have no effect on this mapping. serial interface register map the following table shows the function and address of the various control bits that are loaded through the serial interface during write operations. regname d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1 d0 efault 00h reset x se4 se3 se2 se1 se0 id9 id8 id7 id6 id5 id4 id3 id2 id1 id0 6150h 02h master volume mute x x ml4 ml3 ml2 ml1 ml0 x x x mr4 mr3 mr2 mr1 mr0 8000h 04h lnlvl volume mute x x ml4 ml3 ml2 ml1 ml0 x x x mr4 mr3 mr2 mr1 mr0 8000h 06h master volume mono mutexxxxxxxxxxmm4mm3mm2mm1mm0 8000h 0ah pcbeep volume mute x xxxxxxxxxpv3pv2pv2pv0x 8000h 0ehmic volume mutexxxxxxxx 20db x gn4 gn3 gn2 gn1 gn0 8008h 10h line in volume mute x x gl4 gl3 gl2 gl1 gl0 x x x gr4 gr3 gr2 gr1 gr0 8808h 12h cd volume mute x x gl4 gl3 gl2 gl1 gl0 x x x gr4 gr3 gr2 gr1 gr0 8808h 18h pcm out volume mute x x gl4 gl3 gl2 gl1 gl0 x x x gr4 gr3 gr2 gr1 gr0 8808h 1ahrec select xxxxxsl2sl1sl0xxxxxsr2sr1sr0 0000h 1chrec gain mutexxxgl3gl2gl1gl0xxxxgr3gr2gr1gr0 8000h 20h general purpose pop st 3d ld x x mix ms lpbk xxxxxx x 0000h 26h power/down control status apdxpr5pr4pr3pr2pr1pr0xxxxrefanldacadc 000fh 28h ext?d audio id id1 id0 xxxxamap ldac sdac cdac x x vrm x dra vra 1001h 2ah ext?d audio stat/ctrl x prl prk prj pri x madc ldac sdac cdac x x vrm x dra vra 0000h 2ch front dac rate sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 bb80h 32h audio adc rate sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 bb80h 5ch vendor specific revision x x x x xxxxxxxame 1000h 72h front mixer volume mute x x gl4 gl3 gl2 gl1 gl0 x x x gr4 gr3 gr2 gr1 gr0 0808h 74h surround sound x x xxxxxxxxxxxxdss1dss0 0000h 7ah vendor reserved x x xxxxxxxxxxxxx x 0000h 7ch vendor id1 f7 f6 f5 f4 f3 f2 f1 f0 s7 s6 s5 s4 s3 s2 s1 s0 574dh 7eh vendor id2 t7 t6 t5 t4 t3 t2 t1 t0 rev7 rev6 rev5 rev4 rev3 rev2 rev1 rev0 4c03h table 15 serial interface register map description note: all unused bits should have zeros written to them and will return the same when read.
wm9708 advanced information wolfson microelectronics ltd ai rev 2.0 april 2001 26 recommended external components 3 dvdd dgnd 27 28 vref vrefout agnd avdd dvdd avdd dgnd agnd cap agnd xtlout 5 xtlin 4 pcbeep 12 13 14 15 16 cdl 18 cdgnd cdr mic1 2 mixer inputs sdataout 6 bitclk 7 sdatain 9 sync 10 resetb 11 ac-link dgnd c4 c12 c13 c20 xt c21 c11 c9 c8 c7 c6 c5 c1 notes: 1. c2, c3, c12, c13 and c15 should be as close to wm9708 as possible. 2. agnd and dgnd should be connected as close to wm9708 as possible. c14 c15 c16 22 21 20 stereo output 24 lineoutl 25 lineoutr 26 monoout mono output c17 c18 c19 + + + nc nc nc 23 1 lineinl 17 lineinr 8 19 agnd c10 + + c2 c3 wm9708 + + figure 15 external components diagram
advanced information wm9708 wolfson microelectronics ltd ai rev 2.0 april 2001 27 recommended external components values component reference suggested value description c1 to c4 10nf de-coupling for dvdd and avdd c5 to c17 470nf ac coupling capacitors for setting dc level of analogue inputs to vcap1. value chosen to give corner frequency below 20hz for min 10k input impedance. c18 1 f c19 0.1 f c20 10 f c21 0.1 f c22 10 f reference de-coupling capacitors for adc, dac, mixer and cap2 references. ceramic type or similar. c23 100nf 3d low pass filter. this value sets nominal 100hz. c24 47nf 3d high pass filter. this value sets nominal 1khz. c25 to c29 10 f output ac coupling caps to remove vref dc level from outputs. c30 and c31 22pf optional capacitors for better crystal frequency stability. xt 24.576 mhz ac ? 97 master clock frequency. a bias resistor is not required, but if connected will not affect operation if value is large (above 1m ? ). table 16 external component values recommendations for 3.3v operation the device ? s performance with avdd = 3.3v is shown in electrical characteristics. in 3.3v analogue operation, mid-rail reference scales to 1.5v. all adc and dac references are 3/5 ths of their nominal 5v value. input and output signals that are 1vrms in 5v applications, scale to 660mvrms in 3.3v applications. if 1vrms output is required, the mixer gain adjust pgas need to be increased by 3 times 1.5db steps.
wm9708 advanced information wolfson microelectronics ltd ai rev 2.0 april 2001 28 package dimensions notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.20mm. d. meets jedec.95 mo-150, variation = ah. refer to this specification for further details. dm007.c ds: 28 pin ssop (10.2 x 5.3 x 1.75 mm) symbols dimensions (mm) min nom max a ----- ----- 2.0 a 1 0.05 ----- ----- a 2 1.62 1.75 1.85 b 0.22 ----- 0.38 c 0.09 ----- 0.25 d 9.90 10.20 10.50 e 0.65 bsc e 7.40 7.80 8.20 e 1 5.00 5.30 5.60 l 0.55 0.75 0.95 0 o 4 o 8 o ref: jedec.95, mo-150 a a2 a1 14 1 15 28 e1 e c l gauge plane 0.25 e b d seating plane -c- 0.10 c

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Price & Availability of WOLFSONMICROELECTRONICS-XWM9708CDS

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